1. Field of the Invention
This invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for manufacturing semiconductor devices having twin wells, such as CMOS semiconductor devices and Bi-CMOS semiconductor devices.
2. Description of the Related Art
CMOS semiconductor devices and Bi-CMOS semiconductor devices have P-type and N-type wells formed in a substrate. Such semiconductor devices having two wells of different conductivity types are well known in the art as twin well type semiconductor devices.
In the twin well type semiconductor device, an embedded layer of a conductivity type opposite to that of the substrate is formed below a well of the same conductivity type as that of the substrate in order to prevent occurrence of latch-up phenomenon. For example, in a semiconductor device having a P-type substrate, an N-type embedded layer is formed below a P-type well so as to prevent occurrence of latch-up phenomenon.
In a case where the twin well type semiconductor device is formed, an embedded layer is first formed in the surface area of a substrate by a normal photolithographic technique and ion implantation process. Then, an epitaxial layer is formed on the entire surface of the semiconductor structure, and P-type and N-type wells are sequentially formed in the epitaxial layer. In this case, the P-type well is formed by use of the photolithographic technique and P-type impurity ion implantation process. Likewise, N-type well is formed by use of the photolithographic technique and N-type impurity ion implantation process.
Thus, it is necessary to repeatedly effect the photolithographic process and P-type impurity ion implantation process three times in order to form a twin well type semiconductor device. Such a complicated manufacturing method causes low manufacturing yield and high cost of semiconductor devices.